1. Field of the Invention
The present invention relates to a computer program product, system, and method for determining when to throttle interrupts to limit interrupt processing to an interrupt processing time period.
2. Description of the Related Art
In a dual cluster system, each cluster includes a processing complex and cache. Each cluster is assigned a plurality of volumes, where volumes may be grouped in Logical Subsystems (LSSs). Data being written to a volume may be stored in the cache of the cluster to which the data is assigned. Multiple clusters may receive I/O requests from hosts over a network via a shared network adaptor in the storage controller including the dual clusters.
The shared network adaptor may include a plurality of ports on which I/O requests are received, a plurality of DMA engines to transfer data between the clusters and the ports on which the I/O requests are received, and a plurality of processors (or cores on a single central processing unit) to process I/O requests and control the DMA engines to transfer data for the I/O requests. A processor may be assigned or have affinity for particular ports, so only one processor processes the I/O requests for a port and returns complete or data to the assigned port on which the I/O request was initiated. The DMA engines may have affinity or be assigned to particular logical subsystems (LSSs) or volumes, such that the LSS or volume including the target data of the I/O request is used to determine the DMA engine in the adaptor to use to handle the data transfer to or from the clusters.
The DMA engines in the network adaptor have the ability to detect errors in data being transferred and may signal a processor in the network adaptor, such as a System on a Chip (SOC), of the error by generating an interrupt. In a Symmetric Multiprocessing (SMP) environment, there may be a “master” processor that performs special event handling, such as initializing system hardware and handling system interrupts. If the DMA engines generate numerous error interrupts, a situation may occur where the master processor is processing so many interrupts that it is not able to perform its normal I/O processing operations unrelated to interrupts. If the master processor is involved in handling numerous interrupts, than it may not be able to respond to other of the processors and may appear as in an error state, requiring error recovery. Error recovery is undesirable because it may cause a performance drop while the error recovery is occurring.
Dynamic interrupt coalescing, implemented in Network Interface Cards (NICs) hardware, addresses the problem of interrupt handling overload by coalescing multiple interrupts without signaling the processor. This allows the processor to process several packets before being signaled with an interrupt to process the coalesced interrupts. Coalescing interrupts allows the processor to make progress through its normal, non-interrupt, code path.